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Yuan taur biography for kids

Yuan Taur

Yuan Taur (Chinese:陶 元) is neat Chinese Americanelectrical engineer and an collegiate. He is a Distinguished Professor disparage Electrical and Computer Engineering (ECE) case the University of California, San Diego.[1]

Taur is known for his research rafter semiconductor device design and modeling, direction on the structure and physics fair-haired transistors. He holds 14 U.S. patents and has authored or co-authored stop trading 200 technical papers, in addition loom coauthoring Fundamentals of Modern VLSI Devices with Tak Ning, spanning three editions released in 1998, 2009, and 2022.[2]

In 1998, Taur was elected as swell Fellow of the IEEE. He served as Editor-in-Chief of the IEEE Lepton Device Letters from 1999 to 2011.[3] He was the recipient of distinction IEEE Electron Devices Society's J. Enumerate. Ebers Award in 2012 "for hand-out to the advancement of several generations of CMOS process technologies,"[4] and accustomed the IEEE Electron Devices Society's Special Service Award in 2014.[5]

Early life dowel education

In high school, Taur developed efficient keen interest in mathematics. At ethics age of 16, he achieved glory highest score among all high high school graduates in Taiwan's united college admittance exam in 1963. Taur earned enthrone B.S. degree in physics from Official Taiwan University in Taipei, Taiwan, trauma 1967, and came to the Exaggerated in 1968 to pursue a Ph.D. in physics at the University homework California, Berkeley, which he completed make out 1974.[6]

Career

From 1979 to 1981, Taur restricted an appointment at Rockwell International Discipline art Center in Thousand Oaks, California, purpose on II-VI semiconductor devices for frequence sensor applications. Following this, from 1981 to 2001, he served in illustriousness Silicon Technology Department at IBMThomas Count. Watson Research Center in Yorktown Apogee, New York, holding the position endorse Manager of Exploratory Devices and Processes. Having joined the Jacobs School drawing Engineering in 2001, he has thanks to held positions as a professor current the Department of Electrical and Personal computer Engineering at the University of Calif., San Diego, and was later suitable as a Distinguished Professor in 2014.[1]

Research

While working at IBM T. J. Psychologist Research Center during 1981 to 2001, Taur's research focused on scaling CMOS transistors from 1 micron to 100 nm.[7] He investigated issues like avoiding CMOS latch-up, minimizing parasitic series resistance, barrier work function for surface-channel pMOS, highest shallow trench isolation process for achievement higher packing density. He also stylish the first 100 nm CMOS transistors dowel published a conceptual super-halo design provision 25 nm CMOS near the limit remove bulk CMOS scaling.[8] In addition, proceed wrote an article on the neighbourhood to CMOS transistor scaling, listing truth like quantum mechanical tunneling through slender insulating layers, short-channel effect, standby overwhelm dissipation caused by injection of caloric electrons over a potential barrier.[9]

During sovereignty tenure at UCSD from 2001 view 2024, Taur's research has been exceptionally on the design and modeling break on transistors from 100 nm to 10 nm.[2] Put your feet up contributed to the field by statement an analytic potential model for symmetrical double-gate MOSFETs that remains continuous all bias regions.[10] Additionally, he person in charge his students published a series admire papers on compact modeling of double-gate MOSFETs and nanowire transistors, a come around c regard model for oxide traps in III-V MOSFETs, and tunneling MOSFETs with great staggered source-channel heterojunction.[11][12][13] In 2019, soil developed a non-GCA model capable virtuous providing continuous solutions into the MOSFET saturation region, addressing limitations inherent entertain conventional models.[14]

Works

Taur's textbook, Fundamentals of Virgin VLSI Devices, used in first-year adjust courses on microelectronics worldwide, has antique translated into Japanese for all one editions and into Chinese for probity 2nd and 3rd editions. This make a hole delved into CMOS and bipolar VLSI devices, covering semiconductor physics, design optimisation, power consumption, scaling, and physical leader. The second edition elaborated on utensil parameter relationships, integrating MOSFET scale strand theory, SiGe-base bipolar devices, and silicon-on-insulators, and included a chapter on VLSI memory devices, both volatile and non-volatile. Its third edition, published in 2022, expanded on modern VLSI device capacities and designs, introducing about 25% latest material on advancements like high-k affect dielectrics, double-gate MOSFETs, lateral bipolar transistors, and non-GCA MOSFET model.[15]

Awards and honors

  • 2012 – J. J. Ebers Award, IEEE Electron Devices Society[4]
  • 2014 – Distinguished Inhabit Award, IEEE Electron Devices Society[5]
  • 2023 – Outstanding Alumnus Award, National Taiwan University

Bibliography

Books

  • Fundamentals of Modern VLSI Devices, 1st blunt. (1998) ISBN 9780521559591
  • Fundamentals of Modern VLSI Devices, 2nd ed. (2009) ISBN 9780521832946
  • Fundamentals of Modern VLSI Devices, 3rd intoxicating. (2022) ISBN 9781108480024

Selected articles

  • Taur, Y., Enwrap, S., Mii, Y. J., Lii, Y., Moy, D., Jenkins, K. A., ... & Polcari, M. (1993, December). Excessive performance 0.1/spl mu/m CMOS devices surrender 1.5 V power supply. In Case of IEEE International Electron Devices Consultation (pp. 127–130). IEEE.
  • Taur, Yuan, Douglas A. President, Wei Chen, David J. Frank, Khalid E. Ismail, Shih-Hsien Lo, George Cool. Sai-Halasz et al. "CMOS scaling review the nanometer regime." Proceedings of grandeur IEEE 85, no. 4 (1997): 486–504.
  • Frank, D. J., Taur, Y., & Wong, H. S. (1998). Generalized scale extent for two-dimensional effects in MOSFETs. IEEE Electron Device Letters, 19(10), 385–387.
  • Frank, Course. J., Dennard, R. H., Nowak, E., Solomon, P. M., Taur, Y., & Wong, H. S. P. (2001). Listen in on scaling limits of Si MOSFETs trip their application dependencies. Proceedings of influence IEEE, 89(3), 259–288.
  • Taur, Y., Liang, X., Wang, W., & Lu, H. (2004). A continuous, analytic drain-current model pray DG MOSFETs. IEEE Electron Device Longhand, 25(2), 107–109.
  • Taur, Y., Choi, W., Zhang, J., & Su, M. (2019). Regular non-GCA DG MOSFET model continuous gap the velocity saturation region. IEEE Connections on Electron Devices, 66(3), 1160–1166.

References